Keraunos PCIe Tile
2.0

Architecture & Design:

  • Keraunos System Architecture
    • PCIe Tile Integration in Keraunos-E100 Chiplet Ecosystem
    • Executive Summary
    • Table of Contents
    • 1. System Overview
      • 1.1 Grendel Chiplet Ecosystem
      • 1.2 Keraunos-E100 Role
    • 2. Keraunos-E100 Chiplet Architecture
      • 2.1 High-Level Block Diagram
      • 2.2 Key Subsystems
        • 2.2.1 Chiplet Harness
        • 2.2.2 PCIe Subsystem
        • 2.2.3 HSIO (High-Speed I/O) Tiles
        • 2.2.4 NOC Infrastructure
    • 3. PCIe Tile Position in the System
      • 3.1 PCIe Tile Overview
      • 3.2 Architectural Position
      • 3.3 Key Interfaces
      • 3.4 Model Integration: Host–RC–EP–PCIe Tile Connection Diagram
      • 3.5 VDK Integration: PCIe Tile and Synopsys PCIe Controller in the Virtualizer
        • 3.5.1 VDK Topology
        • 3.5.2 Alignment with Keraunos: Where the PCIe Tile Fits
        • 3.5.3 Interface-Level Connection Diagram (VDK)
        • 3.5.4 Signal- and Interface-Level Mapping (EP ↔ PCIe Tile)
        • 3.5.5 Connection Diagram for Easy Integration
        • 3.5.6 DesignWare PCIe EP and RC Interfaces: Connect to Tile / System vs Stub
    • 4. Connectivity Architecture
      • 4.1 Inbound Data Path (Host → Chip)
      • 4.2 Outbound Data Path (Chip → Host)
      • 4.3 Configuration Path (SMN → PCIe Tile Registers)
      • 4.4 MSI Interrupt Path (Chip → Host)
    • 5. Data Flow Paths
      • 5.1 End-to-End Data Flow Example: Host DMA to Quasar
      • 5.2 Multi-Hop Data Flow: Quasar → PCIe → Host → PCIe → Quasar
    • 6. Address Space Integration
      • 6.1 System Address Map
      • 6.2 PCIe BAR (Base Address Register) Mapping
      • 6.3 Address Translation Stages
    • 7. System Use Cases
      • 7.1 Use Case 1: Model Initialization
      • 7.2 Use Case 2: Inference Execution
      • 7.3 Use Case 3: Package-to-Package Communication
      • 7.4 Use Case 4: System Management
    • 8. Final VDK Platform: Linux-Booting PCIe Tile Integration
      • 8.1 Overview
      • 8.2 Dual-Chiplet VDK Topology
      • 8.3 Host Memory Map
      • 8.4 Device (Keraunos_PCIE_Chiplet) Memory Map
      • 8.5 End-to-End Data Path
      • 8.6 Linux Boot Flow
      • 8.7 PCIe Enumeration
      • 8.8 The pcie_xfer Application
      • 8.9 Device-Side Firmware (pcie_bringup)
      • 8.10 VP Configuration
      • 8.11 Sideband Connections in the Final Platform
    • 9. Appendices
      • 9.1 Acronyms and Abbreviations
      • 9.2 Reference Documents
      • 9.3 Revision History
  • Keraunos PCIe Tile - High-Level Design
    • 1. Introduction
      • 1.1 Purpose
      • 1.2 Scope
      • 1.3 Key Terms
    • 2. Architecture Overview
      • 2.1 Top-Level Architecture
      • 2.2 Design Principles
      • 2.3 System Connection Diagrams
        • 2.3.1 SMN Subsystem Connection
        • 2.3.2 NOC Subsystem Connection
        • 2.3.3 Designware PCIe Controller Connection
        • 2.3.4 System Control Connection
        • TLM Socket Connections (64-bit, blocking transport)
        • Clock Connections
        • Reset Connections
        • CII Interface Connections (Configuration Intercept)
        • Interrupt Forwarding (PCIe Controller → Tile → System)
        • CII Interrupt Output
        • Status Outputs
        • Isolation Control
        • MSI Input (Special Case)
        • Integration Checklist
    • 3. Theory of Operation
      • 3.1 Operational Modes
        • Normal Operation Mode
        • Isolation Mode
        • Bypass Mode
        • Reset Modes
      • 3.2 Initialization and Boot Sequence
      • 3.3 Inbound Data Flow (PCIe to NOC)
      • 3.4 Outbound Data Flow (NOC to PCIe)
      • 3.5 Configuration Access Flow
      • 3.6 MSI Interrupt Generation Flow
      • 3.7 CII Tracking and Configuration Update
      • 3.8 Isolation and Recovery
      • 3.9 Error Handling
      • 3.10 Operating Mode Summary
    • 4. Detailed Block Diagram
      • 3.1 Complete System Architecture
    • 5. Data Flow Paths
      • 4.1 Inbound Data Flow (PCIe → NOC)
      • 4.2 Outbound Data Flow (NOC → PCIe)
      • 4.3 Configuration Access Flow (SMN → Config)
      • 4.4 MSI Generation Flow
      • 4.5 CII Interrupt Flow
    • 6. Module Descriptions
      • 5.1 NOC-PCIE Switch
      • 5.2 Translation Lookaside Buffers
      • 5.3 MSI Relay Unit
      • 5.4 System Information Interface (SII)
    • 7. Address Map
      • 6.1 Inbound Address Routing
      • 6.2 Configuration Address Map
    • 8. Clock and Reset Strategy
      • 7.1 Reset Hierarchy
      • 7.2 Reset Effects
      • 7.3 Isolation Sequence
    • 9. Interface Specifications
      • 8.1 External TLM Sockets
      • 8.2 Control and Status Signals
    • 10. Known Limitations and Findings
      • 9.1 Architecture Limitations
      • 9.2 Documented Findings
    • 11. Test Coverage Summary
      • 10.1 Test Suite Overview
      • 10.2 Coverage Metrics
    • 12. References
      • 11.1 Related Documentation
      • 11.2 Source Code Organization
  • Keraunos PCIE Tile SystemC/TLM2.0 Design Document
    • Sphinx Setup Instructions
      • 1. Install Required Extensions
      • 2. Configure conf.py
      • 3. Build HTML Documentation
      • 4. Alternative: Use make
    • ⭐ Key Implementation Features
    • Table of Contents
    • 1. Introduction
      • 1.1 Purpose
      • 1.2 Scope
      • 1.3 References
      • 1.4 Implementation Version
    • 1.5 Refactored Architecture Overview ⭐ NEW
      • 1.5.1 Why Refactoring Was Necessary
      • 1.5.2 Refactored Architecture Pattern
        • Original Design (Socket-Based):
        • Refactored Design (Function-Based):
      • 1.5.3 Function Callback Communication Pattern
        • Callback Type Definition:
        • Setting Up Callbacks (Wire Components):
        • Benefits of Function Callbacks:
      • 1.5.4 Smart Pointer Memory Management
      • 1.5.5 SCML2 Memory Integration
      • 1.5.6 Temporal Decoupling Support
      • 1.5.7 Modern C++ Best Practices Applied
      • 1.5.8 File Organization
      • 1.5.9 Component Communication Pattern
      • 1.5.10 Null Safety Pattern
      • 1.5.11 Performance Characteristics
      • 1.5.12 Code Example - Complete Transaction Path
    • 2. System Overview
      • 2.1 Keraunos PCIE Tile Context
      • 2.2 Modeled Components
      • 2.3 Design Objectives
    • 3. Architecture
      • 3.1 Overall Structure
      • 3.2 Component Hierarchy
      • 3.3 Data Flow
        • Inbound Traffic Flow
        • Outbound Traffic Flow
        • MSI Flow
    • 4. Component Design
      • 4.1 TLB Common Structures
        • 4.1.1 TlbEntry Structure
      • 4.2 Inbound TLB Design
        • 4.2.1 Overview and Use Cases
        • 4.2.2 TLBSysIn0 - System Management Inbound TLB
        • 4.2.3 TLBAppIn0 - Application Inbound TLB (BAR0/1)
        • 4.2.4 TLBAppIn1 - Application Inbound TLB (BAR4/5)
        • 4.2.5 Inbound TLB Translation Flow
        • 4.2.6 Address Translation Examples
        • 4.2.7 AxUSER Field Format
        • 4.2.8 Configuration and Initialization
        • 4.2.9 Error Handling
        • 4.2.10 Integration with System
      • 4.3 Outbound TLB Design
        • 4.3.1 Overview and Use Cases
        • 4.3.2 TLBSysOut0 - System Management Outbound TLB
        • 4.3.3 TLBAppOut0 - Application Outbound TLB (High Address)
        • 4.3.4 TLBAppOut1 - Application Outbound TLB (DBI Access)
        • 4.3.5 Outbound TLB Translation Flow
        • 4.3.6 Address Translation Examples
        • 4.3.7 Configuration and Initialization
        • 4.3.8 Error Handling
        • 4.3.9 Integration with System
      • 4.4 MSI Relay Unit Design
        • 4.4.1 Overview
        • 4.4.2 Architecture
        • 4.4.3 MSI-X Table Entry
        • 4.4.4 Pending Bit Array (PBA)
        • 4.4.5 MSI Thrower Logic
        • 4.4.6 Register Map
      • 4.5 Intra-Tile Fabric Switch Design
        • 4.5.1 NOC-PCIE Switch
        • 4.5.2 NOC-IO Switch
        • 4.5.3 SMN-IO Switch
      • 4.6 System Information Interface (SII) Block
        • 4.6.1 Overview
        • 4.6.2 Architecture and Operation
        • 4.6.3 CII Tracking Implementation
        • 4.6.4 Register Map
        • 4.6.5 Clock Domain Crossing
        • 4.6.6 Interrupt Generation and Routing
        • 4.6.7 Interface Specification
        • 4.6.8 Implementation Details
      • 4.7 Configuration Register Block
        • 4.7.1 Overview
        • 4.7.2 Status Registers
        • 4.7.3 Isolation Behavior
      • 4.8 Clock & Reset Control Module
        • 4.8.1 Overview
        • 4.8.2 Clock Domains
        • 4.8.3 Reset Sequence
        • 4.8.4 Interface
      • 4.9 PLL/CGM (Clock Generation Module)
        • 4.9.1 Overview
        • 4.9.2 PLL Lock
        • 4.9.3 Interface
      • 4.10 PCIE PHY Model
        • 4.10.1 Overview
        • 4.10.2 Features
        • 4.10.3 Interface
      • 4.11 External Interface Modules
        • 4.11.1 NOC-N Interface
        • 4.11.2 SMN-N Interface
      • 4.12 Top-Level Keraunos PCIE Tile Module
        • 4.12.1 Overview
        • 4.12.2 External Interfaces
        • 4.12.3 Internal Connections
    • 5. Interface Specifications
      • 5.1 TLM2.0 Interfaces
        • 5.1.1 AXI4 Target Socket (Inbound TLBs)
        • 5.1.2 AXI4 Initiator Socket (All TLBs)
        • 5.1.3 APB Target Socket (Configuration)
        • 5.1.4 AXI4-Lite Initiator Socket (MSI Relay)
      • 5.2 SystemC Signals
        • 5.2.1 Control Signals
      • 5.3 Address Translation Interfaces
        • 5.3.1 TLB Lookup Methods
        • 5.3.2 Configuration Methods
    • 6. Implementation Details
      • 6.1 Address Translation Algorithms
        • 6.1.1 Inbound Translation (TLBSysIn0)
        • 6.1.2 Outbound Translation (TLBAppOut0)
      • 6.2 Error Handling
        • 6.2.1 Invalid TLB Entry
        • 6.2.2 Out-of-Range Index
      • 6.3 MSI Relay Unit State Machine
      • 6.4 Threading Model
      • 6.5 Memory Modeling
    • 7. Modeling Approach
      • 7.1 Abstraction Level
      • 7.2 SCML2 Usage
        • 7.2.1 Socket Type Selection Rationale
      • 7.3 TLM2.0 Compliance
      • 7.4 Design Patterns
    • 8. Performance Considerations
      • 8.1 Simulation Performance
      • 8.2 Optimization Opportunities
      • 8.3 Scalability
    • 9. Dependencies and Requirements
      • 9.1 Software Dependencies
      • 9.2 Hardware Dependencies
      • 9.3 Integration Requirements
    • 9. Detailed Implementation Architecture
      • 9.1 Class Hierarchy and Relationships
        • Top-Level Module (Only sc_module):
        • Internal Component Pattern:
      • 9.2 Communication Architecture
        • Transaction Flow Pattern:
      • 9.3 Memory Management Architecture
        • Smart Pointer Ownership Tree:
      • 9.4 Callback Wiring Implementation
        • Complete Wiring Example:
      • 9.5 SCML2 Memory Usage Pattern
        • Configuration Storage Implementation:
      • 9.6 Component Lifecycle
        • Initialization Sequence:
      • 9.7 Transaction Processing Flow
        • Inbound PCIe Transaction Example:
      • 9.8 Routing Decision Implementation
        • NOC-PCIE Switch Routing Logic:
        • Outbound Path and BME (Bus Master Enable):
      • 9.9 TLB Translation Implementation
        • Translation Algorithm (page-mask correction):
      • 9.10 Error Handling Strategy
        • Layered Error Response:
      • 9.11 Configuration Register Implementation
        • Register Access Pattern:
    • 10. Implementation Guide
      • 10.1 Building the Design
        • Prerequisites:
        • Build Commands:
        • Build Output:
      • 10.2 Running Tests
        • Unit Tests (Auto-Generated):
        • Test Coverage:
      • 10.3 Adding New Components
        • Pattern for C++ Class Components:
      • 10.4 Debugging and Troubleshooting
        • Common Issues and Solutions:
        • Debug Tools:
      • 10.5 Performance Tuning
        • Temporal Decoupling Configuration:
        • Adding Timing Annotations:
      • 10.6 Test Development Guide
        • Adding New Test Cases:
      • 10.7 Configuration Management
        • TLB Configuration Example:
      • 10.8 Integration with VDK Platform
        • Module Instantiation in Platform:
      • 10.9 Memory Management Best Practices
        • RAII Pattern (Already Applied):
      • 10.10 Coding Standards Applied
        • Modern C++17 Features Used:
    • 11. Test Infrastructure
      • 11.1 Test Framework Overview
      • 11.2 Test Categories (33 Tests)
      • 11.3 Test Execution Results
      • 11.4 Test API Examples
      • 11.5 Coverage Goals
    • 12. Migration from Original Design
      • 12.1 For Developers Familiar with Original
      • 12.2 API Migration Guide
      • 12.3 Backward Compatibility Notes
    • 13. Known Limitations and Future Work
      • 13.1 Current Limitations
      • 13.2 Future Enhancements
    • 14. Lessons Learned and Best Practices
      • 14.1 Architecture Decisions
      • 14.2 Design Patterns Applied
      • 14.3 Recommendations for Similar Projects
    • Appendix A: Implemented Components Summary
      • A.1 Complete Component List
      • A.2 Component Statistics
      • A.3 SCML Compliance
    • Appendix B: Address Map Summary
      • B.1 TLB Configuration Space
      • B.2 MSI Relay Unit Address Map
      • B.3 SII Block Address Map
      • B.4 Config Register Block Address Map
      • B.5 SMN-IO Switch Address Map
      • B.6 NOC-IO Switch Address Map
      • B.7 NOC-PCIE Switch Routing Map
    • Appendix C: Acronyms and Abbreviations

VDK Platform & Integration:

  • VDK Platform Guide: Linux-Booting Keraunos PCIe Tile
    • 1. Introduction
      • 1.1 What This Platform Demonstrates
    • 2. Platform Architecture
      • 2.1 Two-Chiplet Topology
      • 2.2 PCIe Link Wiring
      • 2.3 PCIE_TILE Interface Connections
    • 3. Memory Maps
      • 3.1 Host_Chiplet CPU Address Space
      • 3.2 Keraunos_PCIE_Chiplet SharedMemoryMap Decode
    • 4. Linux Boot
      • 4.1 Boot Flow
      • 4.2 Device Tree Highlights
      • 4.3 Key Boot Parameters
      • 4.4 Toolchain Requirements
    • 5. PCIe Enumeration and BAR Assignment
      • 5.1 Enumeration Topology
      • 5.2 iATU Configuration
    • 6. Data Transfer Application (pcie_xfer)
      • 6.1 Purpose
      • 6.2 Data Path
      • 6.3 Supported Commands
      • 6.4 EP Auto-Detection
      • 6.5 Building pcie_xfer
    • 7. Bare-Metal Test (pcie_e2e_test)
    • 8. VP Configuration Reference
      • 8.1 Available Configurations
      • 8.2 Critical VPCFG Parameters
      • 8.3 Image Loading
    • 9. Sideband Signal Mapping
      • 9.1 EP ↔ PCIE_TILE Sideband
      • 9.2 Clocks and Resets
      • 9.3 MSI Interrupt Path
    • 10. Troubleshooting
      • 10.1 Host Crashes or Nonsense PC
      • 10.2 PCIe EP Not Detected
      • 10.3 BAR0 Access Returns All-Ones
      • 10.4 Data Mismatch on Read-Back
    • 11. Related Documents

Verification:

  • Keraunos PCIE Tile SystemC/TLM2.0 Testplan
    • Table of Contents
    • 1. Introduction
      • 1.1 Purpose
      • 1.2 Scope
      • 1.3 Test Objectives
      • 1.4 TLB Translation and Sys In/Out (Reference)
      • 1.5 References
    • 1.5 Test Traceability Matrix
    • 2. Test Environment
      • 2.1 Testbench Structure
      • 2.2 Test Components
      • 2.3 Test Tools
    • 3. Test Strategy
      • 3.1 Test Levels
      • 3.2 Test Methodology
      • 3.3 Test Phases
    • 4. Inbound TLB Test Cases
      • 4.1 TLBSysIn0 Test Cases
        • TC_INBOUND_SYS_001: Basic Address Translation
        • TC_INBOUND_SYS_002: Invalid Entry Detection
        • TC_INBOUND_SYS_003: Index Calculation
        • TC_INBOUND_SYS_004: Page Boundary Crossing
        • TC_INBOUND_SYS_005: AxUSER Field Mapping
        • TC_INBOUND_SYS_006: System Ready Bypass
      • 4.2 TLBAppIn0 Test Cases
        • TC_INBOUND_APP0_001: BAR0/1 Translation
        • TC_INBOUND_APP0_002: Multiple Instance Support
        • TC_INBOUND_APP0_003: 16MB Page Size
        • TC_INBOUND_APP0_004: Non-Cacheable and QoSID
      • 4.3 TLBAppIn1 Test Cases
        • TC_INBOUND_APP1_001: BAR4/5 Translation
        • TC_INBOUND_APP1_002: 8GB Page Size
        • TC_INBOUND_APP1_003: DRAM Mapping
    • 5. Outbound TLB Test Cases
      • 5.1 TLBSysOut0 Test Cases
        • TC_OUTBOUND_SYS_001: DBI Access Translation
        • TC_OUTBOUND_SYS_002: 64KB Page Size
        • TC_OUTBOUND_SYS_003: All 16 Entries
      • 5.2 TLBAppOut0 Test Cases
        • TC_OUTBOUND_APP0_001: High Address Translation (>=256TB)
        • TC_OUTBOUND_APP0_002: Address Range Check
        • TC_OUTBOUND_APP0_003: 16TB Page Size
      • 5.3 TLBAppOut1 Test Cases
        • TC_OUTBOUND_APP1_001: Low Address Translation (<256TB)
        • TC_OUTBOUND_APP1_002: DBI Access from Application
    • 6. MSI Relay Unit Test Cases
      • 6.1 Register Access Tests
        • TC_MSI_RELAY_001: MSI Receiver Write
        • TC_MSI_RELAY_002: MSI-X Table Configuration
        • TC_MSI_RELAY_003: Outstanding Count
      • 6.2 MSI Generation Tests
        • TC_MSI_RELAY_004: Basic MSI Generation
        • TC_MSI_RELAY_005: MSI-X Enable Control
        • TC_MSI_RELAY_006: Global Mask Control
        • TC_MSI_RELAY_007: Vector Mask Control
        • TC_MSI_RELAY_008: Invalid Entry Handling
        • TC_MSI_RELAY_009: Multiple Pending Interrupts
        • TC_MSI_RELAY_010: SetIP Signal
        • TC_MSI_RELAY_011: All 16 Vectors
    • 7. Integration Test Cases
      • 7.1 TLB + MSI Relay Integration
        • TC_INTEGRATION_001: MSI-X Table Access via TLB
        • TC_INTEGRATION_002: MSI Generation Through Fabric
      • 7.2 Multiple TLB Integration
        • TC_INTEGRATION_003: Concurrent TLB Operations
        • TC_INTEGRATION_004: Outbound + Inbound Round Trip
    • 8. Switch Test Cases
      • 8.1 NOC-PCIE Switch Test Cases
        • TC_SWITCH_NOC_PCIE_001: Address Routing Based on AxADDR[63:60]
        • TC_SWITCH_NOC_PCIE_002: Status Register Special Routing
        • TC_SWITCH_NOC_PCIE_003: Isolation Support
        • TC_SWITCH_NOC_PCIE_004: Inbound Enable Control
        • TC_SWITCH_NOC_PCIE_005: Bypass Path Routing
        • TC_SWITCH_NOC_PCIE_006: Address Conversion (64-bit to 52-bit)
      • 8.2 NOC-IO Switch Test Cases
        • TC_SWITCH_NOC_IO_001: Local Resource Routing
        • TC_SWITCH_NOC_IO_002: External NOC Routing
        • TC_SWITCH_NOC_IO_003: High Address Routing (AxADDR[51:48])
        • TC_SWITCH_NOC_IO_004: Timeout Detection
      • 8.3 Bus Master Enable (BME) Test Cases
        • TC_BME_001: EP Mode, BME=0 — Memory TLP Blocked
        • TC_BME_002: EP Mode, BME=0 — DBI TLP Allowed
        • TC_BME_003: EP Mode, BME=0 — Config TLP Allowed
        • TC_BME_004: EP Mode, BME=1 — All Traffic Allowed
        • TC_BME_005: RP Mode — All Traffic Allowed Regardless of BME
      • 8.4 SMN-IO Switch Test Cases
        • TC_SWITCH_SMN_IO_001: Address-Based Routing
        • TC_SWITCH_SMN_IO_002: SerDes Routing
        • TC_SWITCH_SMN_IO_003: External SMN Routing
        • TC_SWITCH_SMN_IO_004: Timeout Detection
    • 9. SII Block Test Cases
      • 9.1 Register Access Tests
        • TC_SII_001: Configuration Register Access
        • TC_SII_002: CII Tracking
        • TC_SII_003: Bus/Device Number Assignment
    • 10. Config Register Block Test Cases
      • 10.1 Register Access Tests
        • TC_CONFIG_REG_001: TLB Configuration Space Access
        • TC_CONFIG_REG_002: System Ready Register
        • TC_CONFIG_REG_003: PCIE Enable Registers
        • TC_CONFIG_REG_004: Isolation Behavior
    • 11. Clock & Reset Test Cases
      • 11.1 Clock Generation Tests
        • TC_CLOCK_RESET_001: Reference Clock Generation
        • TC_CLOCK_RESET_002: PCIE Clock Generation
      • 11.2 Reset Sequence Tests
        • TC_CLOCK_RESET_003: Cold Reset Sequence
        • TC_CLOCK_RESET_004: Warm Reset Sequence
        • TC_CLOCK_RESET_005: Isolation Behavior
    • 12. PLL/CGM Test Cases
      • 12.1 PLL Lock Tests
        • TC_PLL_CGM_001: PLL Lock Sequence
        • TC_PLL_CGM_002: PLL Configuration
    • 13. PCIE PHY Test Cases
      • 13.1 PHY Configuration Tests
        • TC_PHY_001: APB Configuration Access
        • TC_PHY_002: AHB Firmware Download
        • TC_PHY_003: Lane Reversal Support
    • 14. External Interface Test Cases
      • 14.1 NOC-N Interface Tests
        • TC_EXTERNAL_NOC_001: Transaction Forwarding
      • 14.2 SMN-N Interface Tests
        • TC_EXTERNAL_SMN_001: Transaction Forwarding
    • 15. Top-Level Integration Test Cases
      • 15.1 Full Tile Integration
        • TC_TOP_LEVEL_001: Complete Reset Sequence
        • TC_TOP_LEVEL_002: End-to-End Transaction Flow
        • TC_TOP_LEVEL_003: MSI End-to-End Flow
        • TC_TOP_LEVEL_004: Isolation Sequence
        • TC_TOP_LEVEL_005: Multiple Clock Domain Operation
    • 16. End-to-End Test Cases
      • 16.1 Inbound Data Paths (PCIe → NOC/SMN)
        • TC_E2E_INBOUND_001: PCIe Read → TLB App0 → NOC-N
        • TC_E2E_INBOUND_002: PCIe Write → TLB App1 → NOC-N
        • TC_E2E_INBOUND_003: PCIe → TLB Sys → SMN-N
        • TC_E2E_INBOUND_004: PCIe Bypass App Path
        • TC_E2E_INBOUND_005: PCIe Bypass Sys Path
      • 16.2 Outbound Data Paths (NOC/SMN → PCIe)
        • TC_E2E_OUTBOUND_001: NOC-N → TLB App Out0 → PCIe
        • TC_E2E_OUTBOUND_002: SMN-N → TLB Sys Out0 → PCIe
        • TC_E2E_OUTBOUND_003: NOC-N → TLB App Out1 → PCIe DBI
      • 16.3 Configuration Paths (SMN → TLB/SII/MSI Config)
        • TC_E2E_CONFIG_001: SMN-N → TLB Config
        • TC_E2E_CONFIG_002: SMN-N → SII Config
        • TC_E2E_CONFIG_003: SMN-N → MSI Relay Config
      • 16.4 MSI Interrupt Flows
        • TC_E2E_MSI_001: MSI Generation → NOC-N
        • TC_E2E_MSI_002: Downstream MSI Input → Processing
      • 16.5 Status Register Access
        • TC_E2E_STATUS_001: Status Register Read (Route 0xE)
        • TC_E2E_STATUS_002: Status Register Disabled Access
      • 16.6 Isolation and Error Handling
        • TC_E2E_ISOLATION_001: Global Isolation
        • TC_E2E_ISOLATION_002: Config Access During Isolation
      • 16.7 Multi-Path Concurrent Traffic
        • TC_E2E_CONCURRENT_001: Simultaneous Inbound + Outbound
        • TC_E2E_CONCURRENT_002: Multiple TLB Simultaneous Access
      • 16.8 Reset and Initialization Sequences
        • TC_E2E_RESET_001: Cold Reset Sequence
        • TC_E2E_RESET_002: Warm Reset Sequence
      • 16.9 Complete Transaction Flows
        • TC_E2E_FLOW_001: PCIe Memory Read → NOC → Memory → Response
        • TC_E2E_FLOW_002: PCIe Memory Write → NOC → Memory → Completion
        • TC_E2E_FLOW_003: NOC Memory Read → PCIe Controller
        • TC_E2E_FLOW_004: SMN Config Write → PCIe DBI
      • 16.10 Error Injection and Recovery
        • TC_E2E_ERROR_001: Invalid TLB Entry
        • TC_E2E_ERROR_002: Timeout Handling
        • TC_E2E_ERROR_003: Address Decode Error
      • 16.11 MSI-X End-to-End Flow
        • TC_E2E_MSIX_001: Complete MSI-X Interrupt Flow
        • TC_E2E_MSIX_002: Multiple Vector Interrupts
      • 16.12 Clock Domain Crossing
        • TC_E2E_CDC_001: AXI Clock → PCIe Clock
      • 16.13 Performance and Stress Tests
        • TC_E2E_PERF_001: Maximum Throughput Test
        • TC_E2E_STRESS_001: Address Space Sweep
        • TC_E2E_STRESS_002: TLB Entry Exhaustion
      • 16.14 Power Management
        • TC_E2E_POWER_001: Isolation Mode Entry/Exit
      • 16.15 System Integration Scenarios
        • TC_E2E_SYSTEM_001: Boot Sequence
        • TC_E2E_SYSTEM_002: Shutdown Sequence
        • TC_E2E_SYSTEM_003: Error Recovery Scenario
      • 16.16 Refactored Architecture Validation
        • TC_E2E_REFACTOR_001: Function Callback Chain
        • TC_E2E_REFACTOR_002: No Internal Sockets Remain
    • 17. Coverage Goals
    • 16. Coverage Goals
      • 16.1 Functional Coverage
        • TLB Coverage
        • MSI Relay Coverage
        • Switch Coverage
        • SII Coverage
        • Config Register Coverage
        • Clock/Reset Coverage
        • PHY Coverage
      • 16.2 Code Coverage
      • 16.3 Specification Coverage
    • 17. Test Infrastructure
      • 9.1 Testbench Components
        • Stimulus Generator
        • Monitor
        • Reference Model
      • 9.2 Test Utilities
      • 9.3 Test Configuration
    • 18. Regression Testing
      • 10.1 Regression Suite
      • 10.2 Regression Criteria
      • 10.3 Continuous Integration
    • Appendix A: Unit/Integration Test Case Summary (Sections 4-15)
    • Appendix A.2: End-to-End Test Case Summary (Section 16) — Implemented in Keranous_pcie_tileTest.cc
    • Appendix B: Test Execution Plan
      • Phase 1: Unit Tests (Weeks 1-3)
      • Phase 2: Functional Tests (Weeks 4-5)
      • Phase 3: Integration Tests (Weeks 6-7)
      • Phase 4: System Tests (Week 8)
      • Phase 5: Regression (Week 9)
  • Enable Gating Feature - Design Documentation
    • Overview
    • Register Interface
    • Implementation
      • Signal Propagation
      • Key Features
    • Test Coverage
Keraunos PCIe Tile
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